DRAM price fell below cash cost due to weak growth in demand leading to future production cut from DRAM makers

DRAM DDR2 1Gb 667MHz spot price fell from a high of 2.29 US$ on May 6th to 1.13 US$ on Oct. 17th for a nearly 50% drop in price.  Since DRAM spot price first fell below the average cash cost of most DRAM makers back in Sep. 6th, given the current inventory level and weakening demand, DRAM maker will have to cut back production much further. Once DDR2 1Gb drops below 1.3 US$, continued production will simply lead to cash loss, and it will be completely pointless to continue producing any longer.

DRAM 512Mb 667MHz also fell below 1.0 US$ near the end of November last year which was close to the average cash cost of most DRAM makers at the time. However, it is different from the current scenario because the lower price helped stimulate demand of onboard memory per PC from 1GB to 2GB and consumed the existing oversupply. In Q208, PC OEMs and most buyers in the spot market, based on the common belief that DRAM price has hit the bottom and was about to rebound, built up their inventory up to a much as a full month and more.  As a result, DRAM DDR2 contract price rose almost 25%, near DRAM makers' average fully loaded cost. 

However, as it seemed that we might finally see a market turnaround, given both the price rise and the continued cost reduction by transitioning to 1Gb dies and 70nm process, Samsung announced in Q208 that it will increase its production in order to reach 100% YoY growth. Meanwhile, Rexchip – a joint venture between Elpida and Powerchip – ramped up its production rapidly to 80k wafers per month. In additional, given the transition to 70nm process during Q2, total worldwide DRAM production increased so much in Q2 that, after August, inventory level at PC OEM, memory module makers, and spot market were near fully loaded. Thus, in September, we saw an effort to lower inventory nearly everywhere in the DRAM market which resulted again in an over-supplied market. 

On Sep.30th , DRAM DDR2 1Gb 667MHz fell 7% in a single day from 1.37 US$ to 1.28 US$.  Rumor has it that certain DRAM makers even offered a super-low price of 1.0 US$/1Gb to specific customer in order to clean out its inventory on hand. 

According to DRAMeXchange, using the month of September as comparison base, the average inventory level at PC OEMs, memory module makers, and other buyers in the spot market can be as high as one month. Given that most buyers wants to reduce instead of increasing inventory, it was not possible to sell all DRAM produced in September and October. Given the weak demand due to both the global recession and the already high DRAM content (2GB or more) per PC, plus the high inventory level cross the board due to over-production, DRAM makers have no alternative except to reduce DRAM production.

According to DRAMeXchange estimate, even without considering current inventory level, there is a 10% or more over-supply in the DRAM market.  If we take the current inventory level into account, it will take at least 1 quarter to absorb all current inventory even DRAM makers reduce production by 30%.  Even at we cut production by 30% for one quarter, as soon as price stabilizes, if any major DRAM makers takes the shortcut and resumes full production, market will return to over-supply and price will drop again.

Therefore, DRAM production must be cut by 20% or more for a prolonged period of more than 1 quarter, along with a slowed production capacity increase and a delayed transition to 5xnm process, before we will see a return to a balance between supply and demand. Only by then, DRAM price can again return to a level above DRAM makers’ total cost. We expect to see such adjustment happening soon although it will depend primarily on how soon DRAM makers can cut production, and it will be difficult to expect a return to profitability anytime soon.

A few key checkpoints for the next 3 to 6 months: (1) once Micron confirms that it will acquire all current Qimonda shares in Inotera, Inotera will transition its technology to Micron technology within 6 months and cease to supply DRAM to Qimonda after 8 months.  As such, we expect Inotera to reduce its capacity by roughly 20%, or 25k wafers/month, during the transition process in the next 6 months.

(2) After Qimonda sold off its stakes in Inotera, its production capacity - estimated at 100k 12" wafers/months - will come mainly from its own plants in Germany and USA in addition to Winbond – Qimonda's contract production partner in Taiwan. How Qimonda re-adjusts its production capacity after it exits the Inotera venture will be a key measurement for how Qimonda will impact the market supply in the next 6 months.

(3) The 3 fabs at ProMOS - Fab2, 3, and 4 – also totaled up to 100k 12" wafers/month in capacity. Given its tight cash position, ProMOS will also need to re-adjust its production plan within the next few months as well.

Given the current average monthly wafer production of 1.24M, DRAMeXchange believes this figure needs to be reduced to at most 1M in order to reduce current inventory level. Given the slowing growth in demand, DRAM supply growth will also needs to slow to 30% or below in order to speed up the recovery in DRAM market.

TSV (Through Silicon VIA): solution for stacking multiple NAND flash dies

Primarily applications of NAND Flash such as memory cards, USB drives, and SSD have begun to see rapid growth in memory capacity requirement. Currently, the maximum capacity of SD and CF memory cards is 32GB and 16GB for micro-SD; several vendors have introduced USB drives with 64GB capacity while most SSD products features 32, 64, 80 and 128GB. We expect SSD capacity to grow up to 256GB or above during 2009-2010.  As the capacity requirement continues to grow, makers of these NAND Flash based products will have to face certain bottleneck in packaging technology.

Currently, the maximum capacity per single NAND Flash die using 5xnm process is 16Gb (=2GB). However, 16Gb dies using 5xnm process will not fit into micro-SD. we need to wait till 4xnm process technology gets mature. However, regardless of whether vendors use 8 5xnm 8Gb die + 1 control IC to make a 8GB micro-SD or 8 4xnm 16Gb die + 1 control IC to make a 16GB micro-SD, vendors will be looking a very crowded space inside the micro-SD package which will impact yield severely given the limited space to wirebond the dies together. Thus, current COB process for high capacity micro-SD often faces yield issues when attempting to stack multiple dies together.

Current SSD package technology uses 8, 10, 16 or 20, etc NAND Flash chips in TSOP package on a single PCB with one die per TSOP. Although TSOP can accommodate much bigger die than micro-SD in terms of area, SSD also faces the same challenge as micro-SD as its capacity is limited to the number of dies each TSOP can hold. For example, if the maximum capacity offered in a single TSOP package is 128Gb (=16GB), SSD makers can use 8 TSOP to make a 128GB SSD.  If SSD maker wishes to make a 256GB SSD, then 16 128Gb chips are needed. If we want to keep stay with 8 TSOP only, each chip will need to contain 256Gb. Neither is possible unless we can achieve finer geometries on each die or new breakthroughs in how we package stacked dies.

Because of the difficulties involved with further miniaturization from 4x nm onward, in order to continue to increase capacity without being impacted by the difficulties in process advancement, vendors can only turn to breakthroughs in packaging technology such as TSV (Through Silicon Via).  TSV is different from conventional wirebond package technology in that it creates vias on the die either by etching or laser, then fill the vias with conducting materials such as copper, polysilicon, tungsten, etc, then finally stack the grinded dies together. TSV is especially advantageous to traditional wirebond because of its shorter signal path, faster data transmission rate, less noise and better performance – all are qualities that contribute to better data transfer between each NAND Flash die and the control IC in memory card application. Currently, major NAND Flash vendors such as Intel, Micron, Samsung, Toshiba, etc have all developed TSV package technology. We expect to see TSV to gain wider usage and even higher capacity in memory cards, USB drives, SSD, etc are required within next 3 to 5 years.

Introduction of new Intel CPU platform will help DRAM transition to new standards

The 45nm DT CPU - Nehalem "Core i7" – announced in early 2008 will finally launch in November.  Intel will also launch the X58 highend chipset in conjunction with the Core i7 simultaneously as older platforms will not be able to support the new technologies built into Core i7 such as QPI, Turbo Mode Operation, integrated memory controller, DDR3 memory support, etc.

The new architecture in Core i7 will help speed up the generation shift from DDR2 to DDR3.  Previous North Bridge chipsets such as widely accepted G31 or highend P45 chipsets allow PC makers to choose between DDR2 and DDR3.  Given the much lower price for DDR2, PC makers are strongly biased to choose DDR2 instead of DDR3 which makes it more difficult for DDR3 to take off as the new memory standard.

However, the Core i7, in addition to an integrated Memory Controller, supports only the DDR3 standard. Thus, DT that supports Core i7 + X58 platform will provide a strong push for popularizing DDR3 standard. Of course, initially, Core i7 + X58 is positioned for highend products and, regardless of the fact that MB supporting DDR3 should cost nearly the same as those supporting DDR2, the overall system cost will be much higher than systems supporting DDR2. Thus, although Core i7+X58 is a push in the right direction, DDR3 penetration in DRAM market will continue to be limited initially.

Subsequently, key to the adoption of DDR3 is still the price difference between DDR3 and DDR2. When market eventually begins to adopt Core i7+X58 by late 2009, DRAM market will receive a strong push to popularizing DDR3. But given the sluggish economic outlook in 2009, adoption to new CPU platform can be delayed from late 2009 to as far back as 2010. Thus, rate of adoption for DDR3 will depend completely on the price difference between DDR3 and DDR2 instead of when DDR3 chipsets are made available, unlike what happened when DDR2 took over from DDR1 previously.