The 256-, 128- and 64MByte modules use 128-Mbit DDR SDRAMs; they conform to the JEDEC standard for 184-pin DIMMs and 200-pin SODIMMs. PC2100/1600 with 133/100 MHz Clock The DDR SDRAMs used in the modules read and write data on both the rising and falling edges of the differntial clock inputs (CLK,/CLK), and they have a 7ns clock cycle time. Therefore, the DDR modules process data at 2.1-GByte/sec (PC2100) or 1.6-Gbyte/sec(PC1600) Bandwidth using 133 MHz or 100 MHz clocks respectively. They use a low power supply voltage(2.5 V for Vdd and Vddq) for fast signaling at reduced power dissipation. The unbuffered DDR modules are the most suitable for desktip and notebook PCs systems and the registered DDR modules minimize bus loading to deliver reliable data transfers at high speed in high capacity systems. Also,they have a x72 data bus for ECC (Error Correcting Code) systems. They use standard 128Mb DDR SDRAMs, which Mosel Vitelic now produces in volume using a proven 0.17-um process. The 128-Mbit chips are packaged in low-cost TSOPs, a benegit of their power efficiency. Mosel Vitelic’s 128-Mbit DDR SDRAM Series Summary Process : 0.17 µm — high volume, low cost per bit Density : 128 Mbit — highest available Organizations : 32Mx4, 16Mx8, 8Mx16 — scalable configurations for modules Banks : Four-bank architecture — for high page-hit rate Bandwidth : Up to 2.1 GB/sec — highest available when used with a 64-bit bus Data Transfer Rate : 266 Mb/sec or 200 Mb/sec — double that of SDRAM Clock Frequency : 133 or 100 MHz — synchronizes with front-side bus Burst Length : 2, 4, 8 — sequential or interleaved for flexibility Random Access Time : 30 ns (with CAS Latency = 2 or 2.5 ns) — high performance Refresh Cycle : 8k cycles / 64 ms — same as SDRAM Power Supply : 2.5 V ± .2 V — low-power operation Package : 400-mil, 66-pin TSOP with JEDEC standard footprint ~~ based on Mosel Vitelic's press release.